The present invention relates to semiconductor packages, and more particularly, to a window-type ball grid array (WBGA) semiconductor package with a chip being mounted over an opening formed through a substrate and electrically connected to the substrate via the opening by bonding wires.
Window-type semiconductor packages are advanced packaging technology, characterized by forming at least an opening penetrating through a substrate, allowing a chip to be mounted over the opening, and electrically connected to the substrate by bonding wires through the opening. One benefit achieved by this window-type package structure is to shorten length of the bonding wires, and thus make electrical transmission or performances between the chip and the substrate more efficiently implemented.
A conventional window-type ball grid array (WBGA) semiconductor package 1 is exemplified with reference to FIGS. 3 and 4A-4C. As shown in FIGS. 3 and 4A, this WBGA semiconductor package 1 is composed of a substrate 10 formed with an opening 100 penetrating through the same; a chip 11 mounted over the opening 100 on an upper surface 101 of the substrate 10 by means of an adhesive 12 in a face-down manner that, an active surface 110 of the chip 11 faces toward the substrate 10 and is partly exposed to the opening 100; a plurality of bonding wires 13 formed through the opening 100 for electrically connecting the active surface 110 of the chip 11 to a lower surface 102 of the substrate 10; a first encapsulant 14 formed on the lower surface 102 of the substrate 10 for filling the opening 100 and encapsulating the bonding wires 13; a second encapsulant 15 formed on the upper surface 101 of the substrate 10 for encapsulating the chip 11, and a plurality of solder balls 16 implanted on the lower surface 102 of the substrate 10 and situated outside the first encapsulant 14
The above conventional WBGA package I has significant drawbacks. As shown in FIGS. 3, 4B and 4C, gaps G may undesirably exist between the active surface 110 of the chip 11 and the upper surface 101 of the substrate 10 at area uncovered by the adhesive 12 and adjacent to the opening 100 of the substrate 10, for example, along two relatively shorter sides of the opening 100 (as shown in FIG. 3). During a molding process for fabricating the second encapsulant 15 on the upper surface 101 of the substrate 10, the chip 11 at positions corresponding to the adhesive-uncovered gaps G lacks for mechanical support from the substrate 10 and thus leads to chip-cracking in response to impact or force generated during molding, which would thereby adversely affects reliability and yield of fabricated package products.
Therefore, the problem to be solved herein is to provide a semiconductor package for allowing a chip to be well supported on a substrate during a molding process for encapsulating the chip, so as to prevent chip cracks from occurrence.
A primary objective of the present invention is to provide a window-type ball grid array (WBGA) semiconductor package, which allows a chip to be firmly supported on a substrate so as to prevent chip cracks during a molding process for encapsulating the chip, thereby assuring reliability and yield of fabricated package products.
In accordance with the above and other objectives, the present invention proposes a WBGA semiconductor package, comprising: a substrate having an upper surface and a lower surface opposed to the upper surface, and formed with at least an opening penetrating through the upper and lower surfaces, wherein a tape attach area is defined on the upper surface of the substrate peripherally around the opening; an adhesive tape (such as a polyimide film) formed with an aperture corresponding in position to the opening of the substrate, and applied over the tape attach area in a manner as to align the aperture of the adhesive tape with the opening of the substrate; at least a chip having an active surface and a non-active surface opposed to the active surface, and mounted over the adhesive tape in a manner that, a conductive area on the active surface of the chip is exposed to the opening of the substrate and the aperture of the adhesive tape, and the adhesive tape is interposed between the active surface of the chip and the upper surface of the substrate to be free of forming gaps between the chip and the substrate; a plurality of bonding wires formed through the opening of the substrate and the aperture of the adhesive tape, so as to electrically connect the conductive area on the active surface of the chip to the lower surface of the substrate by means of the bonding wires; a first encapsulant formed on the lower surface of the substrate for encapsulating the bonding wires and for filling the opening of the substrate and the aperture of the adhesive tape; a second encapsulant formed on the upper surface of the substrate for encapsulating the chip; and a plurality of solder balls implanted on the lower surface of the substrate at area outside the first encapsulant.
The above package structure provides significant benefits. With no gaps being left between the chip and the substrate through the use of the adhesive tape, the chip can be well held in position on the substrate. During the molding process for fabricating the second encapsulant that encapsulates the chip, the adhesive tape and the first encapsulant respectively formed on the upper and lower surfaces of the substrate, can therefore assure the chip to be firmly supported on the substrate without causing cracks of the chip. As compared to the prior art with unsealed gaps between a chip and a substrate uncovered by an adhesive and adjacent to an opening of the substrate and thus inducing chip-cracking, the adhesive tape used in this invention for perfectly adhering the chip to the substrate in a gap-free manner may desirably assure structural intactness of the chip and thus improve reliability and yield of fabricated package products. Moreover, application of the adhesive tape for chip-substrate attachment is relatively simple to implement, which thereby reduces process complexity and fabrication costs for the package structure.